View X40231S16I-BT1_4219513.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? fn8115.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. x40231, x40233, x40235, x40237, x40239 integrated system management ic triple voltage monitors, por, 2 kbit eeprom memory, and single/dual dcp features ? triple voltage monitors ?user programmable threshold voltage ?power-on reset (por) circuitry ?software selectable reset timeout ?manual reset input ? 2-wire industry standard serial interface ? 2 kbit eeprom with writ e protect & block lock tm ? digitally controlled potentiometers (dcp) ?total resistance 256 tap = 100k ?, 100 tap or 64 tap = 10k ? ?nonvolatile wiper position ?write protect function ? single supply operation ?2.7v to 5.5v ? 16 pin soic (300) package ?soic description the x4023x family of integrated system manage- ment ics combine cpu supervisor functions (v cc power-onpower-on reset (por) circuitry, two addi- tional programmable voltage monitor inputs with soft- ware and hardware indicators), integrated eeprom with block lock tm protection and one or two intersil digitally controlled potentiometers (xdcp). all func- tions of the x4023x are accessed by an industry standard 2-wire serial interface. applications the dcp of the x4023x may be utilized to software control analog voltages for: ? lcd contrast, lcd purity, or backlight control. ? power supply settings such as pwm frequency, voltage trimming or margining (temperature offset control). ? reference voltage setting (e.g. ddr-sdram sstl-2) the 2 kbit integrated eeprom may be used to store id, manufacturer data, maintenance data and module definition data. the programmable por circuit insures v cc is stable before reset is removed and protects against brown-outs and power failures. the programmable voltage monitors have on-chip independent reference alarm levels. with separate outputs, the voltage moni- tors can be used for power-on sequencing. block diagram x4023x family selector guide x= 256 tap 100 tap 64 tap 11 31 51 71 1 91 1 data register command decode & control logic sda scl power-on / low voltage cr register protect logic eeprom threshold reset logic 4 generation reset v2mon v cc vtrip 1 v3mon + - 2 kbit reset manual reset (mr) 8 r h r w v2fail wp v3fail array 2 ? 2000 intersil inc., patents pending (vtrip 1,2,3 are user programmable) wiper register r h r w counter 8 - bit nonvolatile memory 256 tap dcp optional 64 or 100 tap dcp v ss vtrip 2 vtrip 3 wiper register counter 8 - bit nonvolatile memory + - ? + data sheet april 11, 2005
2 fn8115.0 april 11, 2005 pin configuration v2mon v3mon nc 3 4 v cc sda r h0 r w0 vss 7 8 v3fail nc 1 14 15 13 16 10 11 9 12 wp 6 nc 2 mr 5 scl reset v2fail 16 pin soic x40231 v2mon v3mon r w1 3 4 v cc sda r h1 nc vss 7 8 v3fail nc 1 14 15 13 16 10 11 9 12 wp 6 nc 2 mr 5 scl reset v2fail 16 pin soic x40233 v2mon v3mon nc 3 4 v cc sda nc nc vss 7 8 v3fail r h2 1 14 15 13 16 10 11 9 12 wp 6 r w2 2 mr 5 scl reset v2fail 16 pin soic x40235 v2mon v3mon nc 3 4 v cc sda r h0 r w0 vss 7 8 v3fail r h2 1 14 15 13 16 10 11 9 12 wp 6 r w2 2 mr 5 scl reset v2fail 16 pin soic x40237 v2mon v3mon r w1 3 4 v cc sda r h1 nc vss 7 8 v3fail r h2 1 14 15 13 16 10 11 9 12 wp 6 r w2 2 mr 5 scl reset v2fail 16 pin soic x40239 single xdcp dual xdcp x40231, x40233, x40235, x40237, x40239
3 fn8115.0 april 11, 2005 x40231 pin assignment soic name function 1nc no connect 2nc no connect 3v3mon v3mon voltage monitor input. v3mon i s the input to a non-invert ing voltage comparator circuit. when the v3mon input is higher than the v trip3 threshold voltage, v3fail makes a transition to a high level. connect v3mon to v ss when not used. 4v3fail v3mon reset output. this open drain output makes a transition to a high level when v3mon is greater than v trip3 and goes low when v3mon is less than vtrip3. there is no delay circuitry on this pin. the v3fail pin requires the use of an external ?pull-up? resistor. 5mr manual reset. mr is a ttl level compatible input. pulling the mr pin active (high) initiates a reset cycle to the reset pin (v cc reset output pin). reset will remain high for time t purst after mr has returned to it?s normally low state. the reset time can be selected using bits pup1 and pup0 in the cr register. the mr pin requires the use of an external ?pull-down? resistor. 6wp write protect control pin. wp pin is a ttl level compatible input. when held high, write protection is enabled. in the enabled state, this pin prevents all nonvolatile ?write? operat ions. also, when the write protection is enabled, and the device block lock feature is active (i.e. the block lock bits are not [0,0]), then no ?write? (volatile or nonvolatile) operations can be performed in the devi ce (including the wiper position of any of the integrated digitally controlled potent iometers (dcps). the wp pin uses an internal ?pull-down? resistor, thus if left floating the write protection feature is disabled. 7scl serial clock. this is a ttl level compatible input pin used to control the serial bus timing for data input and output. 8sda serial data. sda is a bidirectional ttl level compatible pin used to transfer data into and out of the device. the sda pin input buffer is always active (not gated). this pin requires an external pull up resistor. 9 vss ground . 10 nc no connect 11 r h0 connection to end of resistor array for (the 64 tap) dcp. 12 r w0 connection to terminal equivalent to the ?wiper? of a mechanical potentiometer for dcp. 13 v2mon v2mon voltage monitor input. v2mon is the input to a non-inverting voltage compar ator circuit. when the v2mo n input is greater than the v trip2 threshold voltage, v2fail makes a transition to a high level. connect v2mon to v ss when not used. 14 v2fail v2mon reset output. this open drain output makes a transition to a high level when v2mon is greater than v trip2 , and goes low when v2mon is less than v trip2 . there is no power-up reset delay circuitry on this pin. the v2fail pin requires the use of an external ?pull-up? resistor. 15 reset v cc reset output. this is an active high, open drain output which becomes active whenever v cc falls below v trip1 . reset becomes active on power-up and remains active for a time t purst after the power supply stabilizes (t purst can be changed by varying the pup0 and pup1 bits of the internal control register). the reset pin requires the use of an external ?pull-up? resistor. the reset pin can be forced active (high) using the manual reset (mr) input pin. 16 v cc supply voltage. x40231, x40233, x40235, x40237, x40239
4 fn8115.0 april 11, 2005 x40233 pin assignment soic name function 1nc no connect 2nc no connect 3v3mon v3mon voltage monitor input. v3mon is the input to a non-inverting voltage compar ator circuit. when the v3mon input is higher than the v trip3 threshold voltage, v3fail makes a transition to a high level. connect v3mon to v ss when not used. 4v3fail v3mon reset output. this open drain output makes a transition to a high level when v3mon is greater than v trip3 and goes low when v3mon is less than vtrip3. there is no delay circuitry on this pin. the v3fail pin requires the use of an external ?pull-up? resistor. 5mr manual reset. mr is a ttl level compatible input . pulling the mr pin active (high) initiates a reset cycle to the reset pin (v cc reset output pin). reset will remain high for time t purst after mr has returned to it?s normally low state. the reset time can be selected using bits pup1 and pup0 in the cr register. the mr pin requires the use of an external ?pull-down? resistor. 6wp write protect control pin. wp pin is a ttl level compatible input. when held high, write protection is enabled. in the enabled state, this pin prevents all nonvolatile ?write? opera tions. also, when the write protection is enabled, and the device block lock feature is ac tive (i.e. the block lock bits are not [0,0]), then no ?write? (volatile or nonvolatile) operations can be performed in the de vice (including the wiper position of any of the integrated digitally controlled potentiometers (dcps). the wp pin uses an internal ?pull-down? resistor, thus if left floating the write protection feature is disabled. 7scl serial clock. this is a ttl level compatible input pin used to c ontrol the serial bus timing for data input and output. 8sda serial data. sda is a bidirectional ttl level compatible pin used to transfer data into and ou t of the device. the sda pin input buffer is always active (not gated). this pin requires an external pull up resistor. 9 vss ground. 10 r w1 connection to terminal equivale nt to the ?wiper? of a mechanical potentiometer for dcp. 11 r h1 connection to end of resistor array for (the 100 tap) dcp. 12 nc no connect 13 v2mon v2mon voltage monitor input. v2mon is the input to a non-inverting voltage comparat or circuit. when the v2mon input is greater than the v trip2 threshold voltage, v2fail makes a transition to a high level. connect v2mon to v ss when not used. 14 v2fail v2mon reset output. this open drain output makes a transition to a high level when v2mon is greater than v trip2 , and goes low when v2mon is less than v trip2 . there is no power-up reset delay circuitry on this pin. the v2fail pin requires the use of an external ?pull-up? resistor. 15 reset v cc reset output. this is an active high, open drain output which becomes active whenever v cc falls below v trip1 . reset becomes active on power-up and remains active for a time t purst after the power supply stabilizes (t purst can be changed by varying the pup0 and pup1 bits of the internal control register). the reset pin requires the use of an external ?pull-up? resistor. the reset pin can be forced active (high) using the manual reset (mr) input pin. 16 v cc supply voltage. x40231, x40233, x40235, x40237, x40239
5 fn8115.0 april 11, 2005 x40235 pin assignment soic name function 1 r h2 connection to end of resistor array for (the 256 tap) dcp. 2 r w2 connection to terminal equivale nt to the ?wiper? of a mechanical potentiometer for dcp. 3v3mon v3mon voltage monitor input. v3mon is the input to a non-inverting voltage compar ator circuit. when the v3mon input is higher than the v trip3 threshold voltage, v3fail makes a transition to a high level. connect v3mon to v ss when not used. 4v3fail v3mon reset output. this open drain output makes a transition to a high level when v3mon is greater than v trip3 and goes low when v3mon is less than vtrip3. there is no delay circuitry on this pin. the v3fail pin requires the use of an external ?pull-up? resistor. 5mr manual reset. mr is a ttl level compatible input . pulling the mr pin active (high) initiates a reset cycle to the reset pin (v cc reset output pin). reset will remain high for time t purst after mr has returned to it?s normally low state. the reset time can be selected using bits pup1 and pup0 in the cr register. the mr pin requires the use of an external ?pull-down? resistor. 6wp write protect control pin. wp pin is a ttl level compatible input. when held high, write protection is enabled. in the enabled state, this pin prevents all nonvolatile ?write? opera tions. also, when the write protection is enabled, and the device block lock feature is ac tive (i.e. the block lock bits are not [0,0]), then no ?write? (volatile or nonvolatile) operations can be performed in the de vice (including the wiper position of any of the integrated digitally controlled potentiometers (dcps). the wp pin uses an internal ?pull-down? resistor, thus if left floating the write protection feature is disabled. 7scl serial clock. this is a ttl level compatible input pin used to c ontrol the serial bus timing for data input and output. 8sda serial data. sda is a bidirectional ttl level compatible pin used to transfer data into and ou t of the device. the sda pin input buffer is always active (not gated). this pin requires an external pull up resistor. 9 vss ground . 10 nc no connect 11 nc no connect 12 nc no connect 13 v2mon v2mon voltage monitor input. v2mon is the input to a non-inverting voltage comparat or circuit. when the v2mon input is greater than the v trip2 threshold voltage, v2fail makes a transition to a high level. connect v2mon to v ss when not used. 14 v2fail v2mon reset output. this open drain output makes a transition to a high level when v2mon is greater than v trip2 , and goes low when v2mon is less than v trip2 . there is no power-uppower-up reset delay circuitry on this pin. the v2fail pin requires the use of an external ?pull-up? resistor. 15 reset v cc reset output. this is an active high, open drain output which becomes active whenever v cc falls below v trip1 . reset becomes active on power-up and remains active for a time t purst after the power supply stabilizes (t purst can be changed by varying the pup0 and pup1 bits of the internal control register). the reset pin requires the use of an external ?pull-up? resistor. the reset pin can be forced active (high) using the manual reset (mr) input pin. 16 v cc supply voltage. x40231, x40233, x40235, x40237, x40239
6 fn8115.0 april 11, 2005 x40237 pin assignment soic name function 1 r h2 connection to end of resistor array for (the 256 tap) dcp2. 2 r w2 connection to terminal equivale nt to the ?wiper? of a mechanical potentiometer for dcp2. 3v3mon v3mon voltage monitor input. v3mon is the input to a non-inverting voltage compar ator circuit. when the v3mon input is higher than the v trip3 threshold voltage, v3fail makes a transition to a high level. connect v3mon to v ss when not used. 4v3fail v3mon reset output. this open drain output makes a transition to a high level when v3mon is greater than v trip3 and goes low when v3mon is less than vtrip3. there is no delay circuitry on this pin. the v3fail pin requires the use of an external ?pull-up? resistor. 5mr manual reset. mr is a ttl level compatible input. pulling the mr pin active (high) initiates a reset cycle to the reset pin (v cc reset output pin). reset will remain high for time t purst after mr has returned to it?s normally low state. the reset time can be selected using bits pup1 and pup0 in the cr register. the mr pin requires the use of an external ?pull-down? resistor. 6wp write protect control pin. wp pin is a ttl level compatible input. when held high, write protection is enabled. in the enabled state, this pin prevents all nonvolatile ?write? opera tions. also, when the write protection is enabled, and the device block lock feature is ac tive (i.e. the block lock bits are not [0,0]), then no ?write? (volatile or nonvolatile) operations can be performed in the de vice (including the wiper position of any of the integrated digitally controlled potentiometers (dcps). the wp pin uses an internal ?pull-down? resistor, thus if left floating the write protection feature is disabled. 7scl serial clock. this is a ttl level compatible input pin used to c ontrol the serial bus timing for data input and output. 8sda serial data. sda is a bidirectional ttl level compatible pin used to transfer data into and ou t of the device. the sda pin input buffer is always active (not gated). this pin requires an external pull up resistor. 9 vss ground. 10 nc no connect 11 r h0 connection to end of resistor array for (the 64 tap) dcp0. 12 r w0 connection to terminal equivale nt to the ?wiper? of a mechanical potentiometer for dcp0. 13 v2mon v2mon voltage monitor input. v2mon is the input to a non-inverting voltage comparat or circuit. when the v2mon input is greater than the v trip2 threshold voltage, v2fail makes a transition to a high level. connect v2mon to v ss when not used. 14 v2fail v2mon reset output. this open drain output makes a transition to a high level when v2mon is greater than v trip2 , and goes low when v2mon is less than v trip2 . there is no power-uppower-up reset delay circuitry on this pin. the v2fail pin requires the use of an external ?pull-up? resistor. 15 reset v cc reset output. this is an active high, open drain output which becomes active whenever v cc falls below v trip1 . reset becomes active on power-up and remains active for a time t purst after the power supply stabilizes (t purst can be changed by varying the pup0 and pup1 bits of the internal control register). the reset pin requires the use of an external ?pull-up? resistor. the reset pin can be forced active (high) using the manual reset (mr) input pin. 16 v cc supply voltage. x40231, x40233, x40235, x40237, x40239
7 fn8115.0 april 11, 2005 x40239 pin assignment soic name function 1 r h2 connection to end of resistor array for (the 256 tap) dcp2. 2 r w2 connection to terminal equival ent to the ?wiper? of a mechanical potentiometer for dcp2. 3v3mon v3mon voltage monitor input. v3mon is the input to a non-inverting voltage comp arator circuit. when the v3mon input is higher than the v trip3 threshold voltage, v3fail makes a transition to a high level. connect v3mon to v ss when not used. 4v3fail v3mon reset output. this open drain output makes a transition to a high level when v3mon is greater than v trip3 and goes low when v3mon is less than v trip3 . there is no delay circuitry on this pin. the v3fail pin requires the use of an external ?pull-up? resistor. 5mr manual reset. mr is a ttl level compatible input. pulling the mr pin active (high) initiates a reset cycle to the reset pin (v cc reset output pin). reset will remain high for time t purst after mr has returned to it?s normally low state. the reset time can be selected using bits pup1 and pup0 in the cr register. the mr pin requires the use of an external ?pull-down? resistor. 6wp write protect control pin. wp pin is a ttl level compatible input. when he ld high, write protection is enabled. in the enabled state, this pin prevents all nonvolatile ?write? operati ons. also, when the write protection is enabled, and the device block lock feature is acti ve (i.e. the block lock bits are not [0,0]), then no ?write? (volatile or nonvolatile) operations can be pe rformed in the device (including t he wiper position of any of the integrated digitally controlled potentiometers (dcps). the wp pin uses an internal ?pull-down? resistor, thus if left floating the write protection feature is disabled. 7scl serial clock. this is a ttl level compatible input pin used to control the serial bus timing for data input and output. 8sda serial data. sda is a bidirectional ttl level compatible pin used to transfer data into and out of the device. the sda pin input buffer is always active (not gated). this pin requires an external pull up resistor. 9 vss ground. 10 r w1 connection to terminal equival ent to the ?wiper? of a mechanical potentiometer for dcp1. 11 r h1 connection to end of resistor array for (the 100 tap) dcp1. 12 nc no connect 13 v2mon v2mon voltage monitor input. v2mon is the input to a non-inverti ng voltage comparator circuit. when the v2mon input is greater than the v trip2 threshold voltage, v2fail makes a transition to a high level. connect v2mon to v ss when not used. 14 v2fail v2mon reset output. this open drain output makes a transition to a high level when v2mon is greater than v trip2 , and goes low when v2mon is less than v trip2 . there is no power-up reset delay circuitry on this pin. the v2fail pin requires the use of an external ?pull-up? resistor. 15 reset v cc reset output. this is an active high, open drain output which becomes active whenever v cc falls below v trip1 . reset becomes active on power-up and remains active for a time t purst after the power supply stabilizes (t purst can be changed by varying the pup0 and pup1 bits of the internal control register). the reset pin requires th e use of an external ?pull-up? resist or. the reset pin ca n be forced active (high) using the manual reset (mr) input pin. 16 v cc supply voltage. x40231, x40233, x40235, x40237, x40239
8 fn8115.0 april 11, 2005 detailed device description the x4023x combines one or two intersil digitally controlled potentiomete r (xdcp) devices, v cc power-on reset control, v cc low voltage reset control, two supplementary voltage monitors with independent outputs, and in tegrated eeprom with block lock? protection, in one package. the integrated functional- ity of the x4023x lowers sy stem cost, increases reli- ability, and reduces board space requirements. dcps allow for the ?set-and-forget? adjustment during production test or in-system updating via the industry standard 2-wire interface. applying voltage to v cc activates the power-on reset circuit which sets the re set output high, until the supply voltage stabilizes for a period of time (50-300 msec selectable via software). the reset output then goes low. the low voltage reset circuit sets the reset output high when v cc falls below the mini- mum v cc trip point. reset remains high until v cc returns to proper operating level and stabilizes for a period of time (t purst) . a manual reset (mr) input allows the user to externa lly activate the reset output. two supplementary voltage monitor circuits, v2mon and v3mon, continuously compare their inputs to individual trip voltages (independent on-chip voltage references factory set and user programmable). when an input voltage exceeds it?s associated trip level, the corresponding output (v3fail , v2fail ) goes high. when the input voltage beco mes lower than it?s asso- ciated trip level, the corresponding output is driven low. a corresponding binary representation of the two monitor circuit outputs (v2fail and v3fail ) are also stored in latched, vola tile (cr) register bits. the status of these two monitor outputs can be read out via the 2-wire serial port. the bits will remain set, even after the alarm conditi on is removed, allowing advanced recovery algorithms to be implemented. intersil?s unique circuits allow for all internal trip voltages to be individually programmed with high accuracy, either by intersil at final te st or by the user during their production process. some distributors offer v trip reprogramming as a value added service. this gives the designer great flexibility in changing system param- eters, either at the time of manufacture, or in the field. the memory portion of t he device is a cmos serial eeprom array with intersil?s block lock tm protection. this memory may be used to store module manufactur- ing data, serial numbers, or various other system parameters. the eeprom array is internally organized as x 8, and utilizes intersil?s proprietary direct write tm cells providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. the device features a 2-wire interface. principles of operation serial interface serial interface conventions the device supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. the x40 23x operates as a slave in all applications. serial clock and data data states on the sda line can change only while scl is low (see figure 1). sda state changes while scl is high are reserved for indicating start and stop conditions. see figure 1. on power-up of the x4023x, the sda pin is in the input mode. scl sda data stable data change data stable figure 1. valid data changes on the sda bus x40231, x40233, x40235, x40237, x40239
9 fn8115.0 april 11, 2005 serial start condition all commands are preceded by the start condition, which is a high to low transition of sda while scl is high. the device contin uously monitors the sda and scl lines for the start condition and does not respond to any command until this condition has been met. see figure 2. serial stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda while scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. see figure 2. serial acknowledge an acknowledge (ack) is a software convention used to indicate a successful data transfer. the trans- mitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 3 the device will respond with an acknowledge after recognition of a start condition if the correct device identifier bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. in the read mode, the device will transmit eight bits of data, release the sda line, then monitor the line for an acknowledge. if an ac knowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. the device will terminate furt her data transmissions if an acknowledge is not dete cted. the master must then issue a stop condition to place the device into a known state. device internal addressing addressing protocol overview the user addressable internal components of the x4023x can be split up into three main parts: ?one or two digitally controlled potentiometers (dcps) ?eeprom array ?control and status (cr) register scl sda start stop figure 2. valid start and stop conditions data output from transmitter data output from receiver 8 1 9 start acknowledge figure 3. acknowledge response from receiver scl from master x40231, x40233, x40235, x40237, x40239
10 fn8115.0 april 11, 2005 depending upon the operation to be performed on each of these individual part s, a 1, 2 or 3 byte protocol is used. all operations however must begin with the slave address byte being issued on the sda pin. the slave address selects the part of the x4023x to be addressed, and specifies if a read or write operation is to be performed. it should be noted that in order to perform a write oper- ation to either a dcp or the eeprom array, the write enable latch (wel) bit must first be set (see ?bl1, bl0: block lock protection bits - (nonvolatile)? on page 18.) slave address byte following a start condition, the master must output a slave address byte (refer to figure 4). this byte consists of three parts: ?the device type identifier which consists of the most significant four bits of the slave address (sa7 - sa4). the device type identifier must always be set to 1010 in order to select the x4023x. ?the next three bits (sa3 - sa1) are the internal device address bits. setting these bits to 000 internally selects the eeprom array, while setting these bits to 111 selects the dcp structures in the x4023x. the cr register may be selected using the internal device address 010. ?the least significant bit of the slave address (sa0) byte is the r/w bit. this bit defines the operation to be performed on the device being addressed (as defined in the bits sa3 - sa1). when the r/w bit is ?1?, then a read operation is selected. a ?0? selects a write operation (refer to figure 4) nonvolatile write ac knowledge polling after a nonvolatile write command sequence (for either the eeprom array, the non volatile memory of a dcp (nvm), or the cr register) has been correctly issued (including the final stop condition), the x4023x ini- tiates an internal high volt age write cycle. this cycle typically requires 5 ms. during this time, no further read or write commands can be issued to the device. write acknowledge polling is used to determine when this high voltage write cycle has been completed. to perform acknowledge polling, the master issues a start condition followed by a slave address byte. the slave address issued must contain a valid inter- nal device address. the lsb of the slave address (r/w ) can be set to either 1 or 0 in this case. if the device is still busy with the high voltage cycle then no acknowledge will be returned. if the device has completed the write operation, an acknowledge will be returned and the host can then proceed with a read or write operation. (refer to figure 5) digitally controlled potentiometers dcp functionality the x4023x includes one or two independent resistor arrays. for the 64, 100 or 256 tap xdcps, these arrays respectively contain 63, 99 discrete resistive segments that are connected in series. (the 256 tap resistor achieves an equiva lent end to end resistance.) the physical ends of each array are equivalent to the fixed terminals of a mechan ical potentiometer. at one end of the resistor array the terminal connects to the r hx pin (x = 0,1,2).the other end of the resistor array is connected to v ss inside the package. sa6 sa7 sa5 sa3 sa2 sa1 sa0 device type identifier read / sa4 internal address (sa3 - sa1) internally addressed device 000 eeprom array 010 cr register 111 dcp bit sa0 operation 0write 1 read r/w figure 4. slave address format 101 0 write address internal device x40231, x40233, x40235, x40237, x40239
11 fn8115.0 april 11, 2005 at both ends of each arra y and between each resistor segment there is a cmos switch connected between the resistor array and the wiper (r w x ) output. within each individual array, only one switch may be turned on at any one time. these switches are controlled by the wiper counter register (wcr) (see figure 6). the wcr is a volatile register. on power-up of the x4023x, wiper position data is au- tomatically loaded into t he wcr from its associated non volatile memory (nvm) register. the table below shows the initial values of the dcp wcr?s before the contents of the nvm is loaded into the wcr. the data in the wcr is then decoded to select and enable one of the respective fet switches. a ?make before break? sequence is used internally for the fet switches when the wiper is moved from one tap posi- tion to another. hot pluggability figure 7 shows a typical waveform that the x4023x might experience in a hot pluggable situation. on power-up, v cc applied to the x4023x may exhibit some amount of ringing, before it settles to the required value. the device is designed such that the wiper terminal (r wx ) is recalled to the correc t position (as per the last stored in the dcp nvm), when the voltage applied to v cc exceeds v trip1 for a time exceeding t purst (the power-on reset ti me, set in the cr register - see ?control and status register? on page 18.). therefore, if t trans is defined as the time taken for v cc to settle above v trip1 (figure 7): then the desired wiper terminal position is recalled by (a maximum) time: t trans + t purst . it should be noted that t trans is determined by system hot plug conditions. dcp operations in total there are three operations that can be per- formed on any internal dcp structure: ?dcp nonvolatile write ?dcp volatile write ?dcp read ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes high voltage cycle complete. continue command sequence? issue stop no continue normal read or write command sequence proceed yes figure 5. acknowledge polling sequence decoder resistor array r hx fet switches r wx 0 1 2 n wiper register counter non memory volatile (wcr) (nvm) ?wiper? figure 6. dcp internal structure dcp initial values before recall r 0 (64 tap) v h (tap = 63) r 1 (100 tap) v l (tap = 0) r 2 (256 tap) v h (tap = 255) x40231, x40233, x40235, x40237, x40239
12 fn8115.0 april 11, 2005 a nonvolatile write to a dcp will change the ?wiper posi- tion? by simultaneously writing new data to the associ- ated wcr and nvm. therefore, the new ?wiper position? setting is recalled into the wcr after v cc of the x4023x is powered down and then powered back up. a volatile write operation to a dcp however, changes the ?wiper position? by writing new data to the associ- ated wcr only. the contents of the associated nvm register remains unchange d. therefore, when v cc to the device is powered down then back up, the ?wiper position? reverts to that last position written to the dcp using a nonvolatile write operation. both volatile and nonvolatile write operations are exe- cuted using a three byte command sequence: (dcp) slave address byte, instruction byte, followed by a data byte (see figure 9) a dcp read operation allows the user to ?read out? the current ?wiper position? of the dcp, as stored in the associated wcr. this operation is executed using the random address read command sequence, con- sisting of the (dcp) slave address byte followed by an instruction byte and the slave address byte again (refer to figure 10). instruction byte while the slave address byte is used to select the dcp devices, an instruction byte is used to determine which dcp is being addressed. the instruction byte (figure 8) is valid only when the device type identifier and the internal device address bits of the slave address are set to 1010111. in this case, the two least significant bit?s (i1 - i0) of the instruction byte are used to select the particular dcp (0 - 2). in the case of a write to any of the dcps (i.e. the lsb of the slave address is 0), the most signifi- cant bit of the instruction byte (i7), determines the write type (wt) performed. if wt is ?1?, then a nonv olatile write to the dcp occurs. in this case, the ?wiper position? of the dcp is changed by simultaneously writing new data to the associated wcr and nvm. therefore, the new ?wiper position? setting is recalled into the wcr after v cc of the x4023x has been powered down then powered back up. if wt is ?0? then a dcp volatile write is performed. this operation changes the dcp ?wiper position? by writing new data to the associated wcr only. the contents of the associated nvm register remains unchanged. therefore, when v cc to the device is powered down then back up, the ?wiper position? reverts to that last writte n to the dcp using a nonvol- atile write operation. figure 7. dcp power-up t v cc v trip1 v cc (max.) t purst maximum wiper recall time 0 t trans wt ? description 0 select a volatile write operation to be performed on the dcp pointed to by bits p1 and p0 1 select a nonvolatile write operation to be per- formed on the dcp pointed to by bits p1 and p0 0 0 wt 0 0 0 p1 p0 write type dcp select ? this bit has no effect when a read operation is being performed. i5 i6 i7 i4 i3 i2 i1 i0 figure 8. instruction byte format x40231, x40233, x40235, x40237, x40239
13 fn8115.0 april 11, 2005 dcp write operation a write to dcpx (x=0,1,2) can be performed using the three byte command sequence shown in figure 9. in order to perform a write operation on a particular dcp, the write enable latch (wel) bit of the cr reg- ister must first be set (see ?bl1, bl0: block lock pro- tection bits - (nonvolatile)? on page 18.) the slave address byte 10101110 specifies that a write to a dcp is to be conducted. an acknowl- edge is returned by the x4023x after the slave address, if it has been received correctly. next, an instruction byte is issued on sda. bits p1 and p0 of the instruction byte determine which wcr is to be written, while th e wt bit determines if the write is to be volatile or nonvolatile. if the instruction byte format is valid, another acknowledge is then returned by the x4023x. following the instruction byte , a data byte is issued to the x4023x over sda. the data byte contents is latched into the wcr of the dcp on the first rising edge of the clock signal, after the lsb of the data byte (d0) has been issued on sda (see figure 34). the data byte determines the ?wiper position? (which fet switch of the dcp resistive array is switched on) of the dcp. the maximum value for the data byte depends upon which dcp is being addressed (see fol- lowing table). using a data byte larger than the values specified above results in the ?wiper terminal? being set to the highest tap position. the ?wiper position? does not roll-over to the lo west tap position. for dcp0 (64 tap) and dcp2 (256 tap), the data byte maps one to one to the ?wiper position? of the dcp ?wiper terminal?. therefore, the data byte 00001111 (15 10 ) corresponds to setting the ?wiper ter- minal? to tap position 15. similarly, the data byte 00011100 (28 10 ) corresponds to setting the ?wiper ter- minal? to tap position 28. the mapping of the data byte to ?wiper position? data for dcp1 (100 tap), is shown in ?appendix 1? . an example of a simple c language function which ?translates? between the tap position (decimal) and the data byte (binary) for dcp1, is given in ?appendix 2? . it should be noted that all writes to any dcp of the x4023x are random in nature. therefore, the data byte of consecutive write operations to any dcp can differ by an arbitrary number of bits. also, setting the bits p1 = 1, p0 = 1 is a reserved sequence, and will result in no acknowledge after sending an instruc- tion byte on sda. the factory default setting of all ?wiper position? set- tings is with 00h stored in the nvm of the dcps. this corresponds to having the ?wiper terminal? r wx (x = 0,1,2) at the ?lowest? tap position, therefore, the resistance between r wx and r lx is a minimum (essentially only the wiper resistance, r w ). s t a r t 10101110 a c k wt 0 0 0 0 0 p1 p0 a c k s t o p a c k d7 d6 d5 d4 d3 d2 d1 d0 slave address byte instruction byte data byte figure 9. dcp write command sequence p1- p0 dcpx # taps max. data byte 00 x = 0 64 3fh 0 1 x = 1 100 refer to appendix 1 1 0 x = 2 256 ffh 11 reserved x40231, x40233, x40235, x40237, x40239
14 fn8115.0 april 11, 2005 dcp read operation a read of dcpx (x = 0,1,2) can be performed using the three byte random read command sequence shown in figure 10. the master issues the start condition and the slave address byte 10101110 which specifies that a ?dummy? write? is to be c onducted. this ?dummy? write operation sets which dcp is to be read (in the preced- ing read operation). an acknowledge is returned by the x4023x after the sl ave address if received cor- rectly. next, an instruction byte is issued on sda. bits p1-p0 of the instruction byte determine which dcp ?wiper position? is to be read. in this case, the state of the wt bit is ?don?t care?. if the instruction byte format is valid, then another ac knowledge is returned by the x4023x. following this acknowledg e, the master immedi- ately issues another start condition and a valid slave address byte with the r/w bit set to 1. then the x4023x issues an acknowledge followed by data byte, and finally, the master issues a stop condition. the data byte read in this operation, corresponds to the ?wiper position? (value of the wcr) of the dcp pointed to by bits p1 and p0. it should be noted that when reading out the data byte for dcp0 (64 tap), the upper two most significant bits are ?unknown? bits. for dcp1 (100 tap), the upper most significant bit is an ?unknown?. for dcp2 (256 tap) however, all bits of the data byte are relevant (see figure 10). 2 kbit eeprom array operations on the 2 kbit eeprom array, consist of either 1, 2 or 3 byte command sequences. all opera- tions on the eeprom must begin with the device type identifier of the slave address set to 1010000. a read or write to the eeprom is selected by setting the lsb of the slave address to the appropriate value r/w (read = ?1?, write = ?0?). in some cases when performing a read or write to the eeprom, an address byte may also need to be specified. this address byte can contain the values 00h to ffh. slave address instruction byte a c k a c k s t a r t s t o p slave address data byte a c k s t a r t sda bus signals from the slave signals from the master figure 10. dcp read sequence ?dummy? write read operation 101 1110 0 00 00 0 w t p 1 p 0 101 1111 0 write operation - -- msb lsb dcpx x = 0 x = 1 x = 2 ?-? = don?t care s t a r t s t o p slave address address byte data byte a c k a c k a c k sda bus signals from the slave signals from the master figure 11. eeprom byte write sequence internal device address 1 01 0 0 0 0 0 write operation x40231, x40233, x40235, x40237, x40239
15 fn8115.0 april 11, 2005 eeprom byte write in order to perf orm an eeprom byte write operation to the eeprom array, the write enable latch (wel) bit of the cr register must first be set (see ?bl1, bl0: block lock protection bits - (nonvolatile)? on page 18.) for a write operation, the x4023x requires the slave address byte and an address byte. this gives the master access to any one of the words in the array. after receipt of the address byte, the x4023x responds with an acknow ledge, and awaits the next eight bits of data. after receiving the 8 bits of the data byte, it again responds with an acknowl- edge. the master then terminates the transfer by generating a stop condition, at which time the x4023x begins the internal write cycle to the nonvola- tile memory (see figure 11). during this internal write cycle, the x4023x inputs are disabled, so it does not respond to any requests from the master. the sda output is at high impedance. a write to a region of eeprom memory which has been protecte d with the block-lock feature (see ?bl1, bl0: block lock protec- tion bits - (nonvolatile)? on page 18.), suppresses the acknowledge bit after the address byte. eeprom page write in order to perform an eeprom page write operation to the eeprom array, the write enable latch (wel) bit of the cr register must first be set (see ?bl1, bl0: block lock protection bits - (nonvolatile)? on page 18.) the x4023x is capable of a page write operation. it is initiated in the same manner as the byte write opera- tion; but instead of terminating the write cycle after the first data byte is transfer red, the master can transmit an unlimited number of 8-bit bytes. after the receipt of each byte, the x4023x responds with an acknowl- edge, and the address is internally incremented by one. the page address remains constant. when the counter reaches the end of the page, it ?rolls over? and goes back to ?0? on the same page. for example, if the master writes 12 bytes to the page starting at location 11 (dec imal), the first 5 bytes are written to locations 11 through 15, while the last 7 bytes are written to locations 0 through 6. afterwards, the address counter would point to location 7. if the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time (see figure 13). the master terminates the data byte loading by issu- ing a stop condition, which causes the x4023x to begin the nonvolatile write cycle. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. see figure 12 fo r the address, acknowledge, and data transfer sequence. stops and eeprom write modes stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and receiving the subsequent acknowledge signal. if the master issues a stop within a data byte, or before the x4023x issues a corresponding acknowledge, the x4023x cancels the write oper- ation. theref ore, the contents of the eeprom array does not change. eeprom array read operations read operations are initiated in the same manner as write operations with th e exception that the r/w bit of the slave address byte is set to one. there are three basic read opera tions: current eeprom address read, random eeprom re ad, and sequential eeprom read. s t a r t s t o p slave address address byte data (n) a c k a c k a c k sda bus signals from the slave signals from the master data (1) a c k (2 < n < 16) figure 12. eeprom pa ge write operation 10100000 x40231, x40233, x40235, x40237, x40239
16 fn8115.0 april 11, 2005 current eeprom address read internally the device contains an address counter that maintains the address of the last word read incre- mented by one. therefore, if the last read was to address n, the next read operation would access data from address n+1. on power-up, the address of the address counter is undefined, requiring a read or write operation for initialization. upon receipt of the slave address byte with the r/w bit set to one, the devic e issues an acknowledge and then transmits the eight bits of the data byte. the master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition (see figure 14 for the address, acknowledge, and data trans- fer sequence). it should be noted that the ninth clock cycle of the read operation is not a ?don?t care.? to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. another important point to note regarding the ?current eeprom address read? , is that this operation is not available if the last exec uted operation was an access to a dcp or the cr register (i.e.: an operation using the device type identifier 1010111 or 1010010). immediately after an operation to a dcp or cr regis- ter is performed, only a ?random eeprom read? is available. immediately following a ?random eeprom read? , a ?current eepr om address read? or ?sequential eeprom read? is once again available (assuming that no access to a dcp or cr register occur in the interim). random eeprom read random read operation allows the master to access any memory location in the ar ray. prior to issuing the slave address byte with the r/w bit set to one, the master must first perform a ?dummy? write operation. the master issues the start condition and the slave address byte, receives an acknowledge, then issues an address byte. this ?dummy? write operation sets the address pointer to the address from which to begin the random eepr om read operation. after the x4023x acknowledges the receipt of the address byte, the master immediately issues another start condition and the slave address byte with the r/w bit set to one. this is followed by an acknowl- edge from the x4023x and then by the eight bit word. address address 11 5 bytes 15 7 bytes address = 6 address pointer ends here addr = 7 figure 13. example: writing 12 bytes to a 16-byte page starting at location 11. 5 bytes 10 10 10 10 s t a r t s t o p slave address data a c k sda bus signals from the slave signals from the master figure 14. current eeprom address read sequence 10 1 00001 x40231, x40233, x40235, x40237, x40239
17 fn8115.0 april 11, 2005 the master terminates the read operation by not responding with an acknowledge and instead issuing a stop condition (refer to figure 15). a similar operation called ?set current address? also exists. this operation is pe rformed if a stop is issued instead of the second start shown in figure 15. in this case, the device sets the address pointer to that of the address byte, and then goes into standby mode after the stop bit. all bus activity will be ignored until another start is detected. sequential eeprom read sequential reads can be initiated as either a current address read or random address read. the first data byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. the x4023x con- tinues to output a data byte for each acknowl- edge received. the master terminates the read operation by not responding with an acknowledge and instead issuing a stop condition. the data output is sequential, with the data from address n followed by the data from address n + 1. the address counter for read operations increments through the entire memory contents to be serially read during one operation. at the end of the address space the counter ?rolls over? to address 00h and the device continues to output data for each acknowledge received (refer to figure 16). slave address address byte a c k a c k s t a r t s t o p slave address data a c k s t a r t sda bus signals from the slave signals from the master figure 15. random eeprom address read sequence 0 1 0 0 0 0 1 1 0 1 0 0 0 0 write operation ?dummy? write read operation 01 data (2) s t o p slave address data (n) a c k a c k sda bus signals from the slave signals from the master 1 data (n-1) a c k a c k (n is any integer greater than 1) data (1) figure 16. sequential eeprom read sequence 0 0 0 x40231, x40233, x40235, x40237, x40239
18 fn8115.0 april 11, 2005 control and status register the control and status (cr) register provides the user with a mechanism for changing and reading the status of various parameters of the x4023x (see figure 17). the cr register is a combination of both volatile and nonvolatile bits. the nonvolatile bits of the cr register retain their stored values even when v cc is powered down, then powered back up. the volatile bits how- ever, will always power-up to a known logic state ?0? (irrespective of their value at power-down). a detailed description of the function of each of the cr register bits follows: wel: write enable latch (volatile) the wel bit controls the write enable status of the entire x4023x device. this bit must first be enabled before any write operation (to dcps, eeprom mem- ory array, or the cr register). if the wel bit is not first enabled, then any proceeding (volatile or nonvolatile) write operation to dcps, eeprom array, as well as the cr register, is aborted and no acknowledge is issued after a data byte. the wel bit is a volatile latch that powers up in the disabled, low (0) state. th e wel bit is enabled / set by writing 00000010 to the cr register. once enabled, the wel bit remains set to ?1? until either it is reset to ?0? (by writing 00000000 to the cr register) or until the x4023x powers down, and then up again. writes to the wel bit do not cause an internal high voltage write cycle. therefore, the device is ready for another operation immediately after a stop condition is executed in the cr write command sequence (see figure 18). rwel: register write en able latch (volatile) the rwel bit controls the (cr) register write enable status of the x4023x. therefore, in order to write to any of the bits of the cr register (except wel), the rwel bit must first be set to ?1?. the rwel bit is a volatile bit that powers up in the disabled, low (?0?) state. it must be noted that the rwel bit can only be set, once the wel bit has first been enabled (see "cr register write operation"). the rwel bit will reset itself to the default ?0? state, in one of three cases: ?after a successful write operation to any bits of the cr register has been completed (see figure 18). ?when the x4023x is powered down. ?when attempting to write to a block lock protected region of the eeprom memory (see "bl1, bl0: block lock protection bits - (nonvolatile)", below). bl1, bl0: block lock prot ection bits - (nonvolatile) the block lock protection bits (bl1 and bl0) are used to: ?inhibit a write operation from being performed to cer- tain addresses of the eeprom memory array ?inhibit a dcp write operation (changing the ?wiper position?). the region of eeprom memory which is protected / locked is determined by the combination of the bl1 and bl0 bits written to the cr register. it is possible to lock the regions of eeprom memory shown in the table below: if the user attempts to perform a write operation on a protected region of eepr om memory, the operation is aborted without changing any data in the array. bit(s) description wel write enable latch bit rwel register write enable latch bit v2fs v2mon output flag status v3fs v3mon output flag status bl1 - bl0 sets the block lock partition pup1 - pup0 sets the power-on reset time pup1 wel pup0 cs5 cs6 cs7 cs4 cs3 cs2 cs1 cs0 v3fs v2fs bl0 bl1 rwel figure 17. cr register format nv nv nv nv note: bits labelled nv are nonvolatile (see ?control and status register?). bl1 bl0 protected addresses (size) partition of array locked 0 0 none (default) none (default) 01 c0 h - ff h (64 bytes ) upper 1/4 10 80 h - ff h (128 bytes ) upper 1/2 11 00 h - ff h (256 bytes) all x40231, x40233, x40235, x40237, x40239
19 fn8115.0 april 11, 2005 when the block lock bits of the cr register are set to something other than bl1 = 0 and bl0 = 0, then the ?wiper position? of the dcps cannot be changed - i.e. dcp write operations cannot be conducted: the factory default setting for these bits are bl1 = 0, bl0 = 0. important note: if the write protect (wp) pin of the x4023x is active (high), then all nonvolatile write operations to both th e eeprom memory and dcps are inhibited, irrespective of the block lock bit settings (see "wp: write protection pin"). pup1, pup0: power-on reset bits ? (nonvolatile) applying voltage to v cc activates the power-on reset circuit which holds reset ou tput high, until the sup- ply voltage stabilizes above the v trip1 threshold for a period of time, t purst (see figure 30). the power-on reset bits, pup1 and pup0 of the cr register determine the t purst delay time of the power- on reset circuitry (see "voltage monitoring functions"). these bits of the cr register are non- volatile, and therefore powe r-up to the last written state. the nominal power-on reset delay time can be selected from the following table, by writing the appro- priate bits to the cr register: the default for these bits are pup1 = 0, pup0 = 1. v2fs, v3fs: voltage monito r status bits (volatile) bits v2fs and v3fs of the cr register are latched, volatile flag bits which indicate the status of the volt- age monitor reset output pins v2fail and v3fail . at power-up the vxfs (x=2,3) bits default to the value ?0?. these bits can be set to a ?1? by writing the appro- priate value to the cr register. to provide consistency between the vxfail and v xfs however, the status of the v xfs bits can only be set to a ?1? when the corre- sponding vxfail output is high. once the vxfs bits have b een set to ?1?, they will be reset to ?0? if: ?the device is powered down, then back up, ?the corresponding v xfail output becomes low. cr register write operation the cr register is accessed using the slave address set to 1010010 (refer to figure 4). following the slave address byte, acce ss to the cr register requires an address byte which must be set to ffh. only one data byte is allowed to be written for each cr register write operation. the user must issue a stop, after sending th is byte to the register, to initiate the nonvolatile cycle that stores the bp1, bp0, pup1 and pup0 bits. the x4023x will not acknowledge any data bytes written after the first byte is entered (refer to figure 18). bl1 bl0 dcp write operation permissible 0 0 yes (default) 01 no 10 no 11 no pup1 pup0 power-on reset delay (t pureset ) 00 50ms 0 1 100ms (default) 1 0 200ms 1 1 300ms s t a r t 1 010010r/w a c k 11111 1 11 a c k scl sda s t o p a c k cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 slave address byte address byte cr register data in figure 18. cr register write command sequence x40231, x40233, x40235, x40237, x40239
20 fn8115.0 april 11, 2005 prior to writing to the cr register, the wel and rwel bits must be set using a two step process, with the whole sequence requiring 3 steps ?write a 02h to the cr register to set the write enable latch (wel). this is a volatile operation, so there is no delay after the write. (operation preceded by a start and ended with a stop). ?write a 06h to the cr register to set the register write enable latch (rwel) and the wel bit. this is also a volatile cycle. the zeros in the data byte are required. (operation preceded by a start and ended with a stop). ?write a one byte value to the cr register that has all the bits set to the desired state. the cr register can be represented as qxyst01r in binary, where xy are the voltage monitor output status (v2fs and v3fs) bits, st are the block lock protection (bl1 and bl0) bits, and qr are the power-on reset delay time (t purst ) control bits (pup1 - pup0). this operation is pro- ceeded by a start and ended with a stop bit. since this is a nonvolatile write cycle, it will typically take 5ms to complete. the rwel bit is reset by this cycle and the sequence must be repeated to change the nonvol- atile bits again. if bit 2 is set to ?1? in this third step (qxys t11r) then the rwel bit is set, but the v2fs, v3fs, pup1, pup0, bl1 and bl0 bits remain unchanged. writing a second byte to the control register is not allowed. doing so aborts the write operation and the x4023x does not return an acknowledge. for example, a sequence of writes to the device cr register consisting of [02h, 06h, 02h] will reset all of the nonvolatile bits in the cr register to ?0?. it should be noted that a write to any nonvolatile bit of cr register will be ignored if the write protect pin of the x4023x is active (high) (see "wp: write protec- tion pin"). cr (control) register read operation the contents of the cr register can be read at any time by performing a random read (see figure 18). using the slave address byte set to 10100101, and an address byte of ffh. only one byte is read by each register read operation. the x4023x resets itself after the first byte is read. the master should supply a stop condition to be consis tent with the bus protocol. after setting the wel and / or the rwel bit(s) to a ?1?, a cr register read operation may o cc ur, without inter- rupting a proceeding cr register write operation. data protection there are a number of levels of data protection fea- tures designed into the x4023x. any write to the device first requires setting of the wel bit in the cr register. a write to the cr register itself, further requires the setting of the rwel bit. block lock pro- tection of the device enables the user to inhibit writes to certain regions of th e eeprom memory, as well as to all the dcps. one further level of data protection in the x4023x, is incorporated in the form of the write protection pin. wp: write protection pin when the write protection (wp) pin is active (high), it disables nonvolatile write operations to the x4023x. the table below (x4023x write permission status) summarizes the effect of the wp pin (and block lock), on the write permission status of the device. additional data protection features in addition to the preceding features, the x4023x also incorporates the following data protection functionality: ?the proper clock count and data bit sequence is required prior to the stop bit in order to start a nonvol- atile write cycle. voltage monitoring functions v cc monitoring the x4023x monitors the supply voltage and drives the reset output high (using an external ?pull up? resis- tor) if v cc is lower than v trip1 threshold. the reset output will remain high until v cc exceeds v trip1 for a minimum time of t purst . after this time, the reset pin is driven to a low state. see figure 30. for the power-on / low voltage reset function of the x4023x, the reset output may be driven high down to a v cc of 1v (v rvalid ). see figure 30. another fea- ture of the x4023x, is that the value of t purst may be selected in software via the cr register (see ?pup1, pup0: power-on reset bi ts ? (nonvolatile)? on page 19.). it is recommended to stop communication to the device while reset is high . also, setting the manual reset (mr) pin high overrides the power-on / low voltage circuitry and forc es the reset output pin high (see "mr: manual reset"). x40231, x40233, x40235, x40237, x40239
21 fn8115.0 april 11, 2005 mr: manual reset the reset output can be forced high externally using the manual reset (mr) input. mr is a de-bounced, ttl compatible input, and so it may be operated by con- necting a push-button directly from v cc to the mr pin. reset remains high for time t purst after mr has returned to its low state (see figure 19). an exter- nal ?pull down? resistor is required to hold this pin (normally) low. x4023x write permission status mr reset v cc 0 volts 0 volts t purst figure 19. manual reset response 0 volts v trip1 slave address address byte a c k a c k s t a r t s t o p slave address data a c k s t a r t sda bus signals from the slave signals from the master figure 20. cr register read command sequence 0 1 0 0 1 0 1 1 0 1 0 0 1 0 write operation ?dummy? write read operation cs7 ? cs0 01 block lock bits wp dcp volatile write permitted dcp nonvolatile write permitted write to eeprom permitted write to cr register permitted bl0 bl1 volatile bits nonvolatile bits x1 1 no no no yes no 1x 1 no no no yes no 0 0 1 yes no no yes no x 1 0 no no not in locked region yes yes 1 x 0 no no not in locked region yes yes 0 0 0 yes yes yes (all array) yes yes x40231, x40233, x40235, x40237, x40239
22 fn8115.0 april 11, 2005 v2mon monitoring the x4023x asserts the v2fail output high if the voltage v2mon exceeds the corresponding v trip2 threshold (see figure 21). the bit v2fs in the cr reg- ister is then set to a ?0? (assuming that it has been set to ?1? after syste m initialization). the v2fail output may remain active high with v cc down to 1v. (see figure 21) v3mon monitoring the x4023x asserts the v3fail output high if the voltage v3mon exceeds the corresponding v trip3 threshold (see figure 21). the bit v3fs in the cr reg- ister is then set to a ?0? (assuming that it has been set to ?1? after syste m initialization). the v3fail output may remain active high with v cc down to 1v. v tripx thresholds (x = 1,2,3) the x4023x is shipped with pre-programmed thresh- old (v tripx ) voltages. in applications where the required thresholds are different from the default val- ues, or if a higher precision / tolerance is required, the x4023x trip points may be adjusted by the user, using the steps detailed below. setting a v tripx voltage (x = 1,2,3) there are two procedures used to set the threshold voltages (v tripx ), depending if the threshold voltage to be stored is higher or lower than the present value. for example, if the present v tripx is 2.9 v and the new v tripx is 3.2 v, the new voltage can be stored directly into the v tripx cell. if however, the new setting is to be lower than the present setting, then it is necessary to ?reset? the v tripx voltage before setting the new value. figure 21. voltage monitor response vx vxfail 0v 0v v tripx (x = 2,3) 0 volts v trip1 v cc 01234567 scl sda a0h 01234567 wp v p 01234567 v tripx v2mon, 01h ? sets v trip1 figure 22. setting v tripx to a higher level (x = 1,2,3). 09h ? sets v trip2 0dh ? sets v trip3 data byte ? v cc 00h s t a r t ? ? all others reserved. v3mon x40231, x40233, x40235, x40237, x40239
23 fn8115.0 april 11, 2005 setting a higher v tripx voltage (x = 1,2,3) to set a v tripx threshold to a new voltage which is higher than the present thres hold, the user must apply the desired v tripx threshold voltage to the correspond- ing input pin (v cc , v2mon or v3mon). then, a pro- gramming voltage (vp) must be applied to the wp pin before a start condition is set up on sda. next, issue on the sda pin the slave addr ess a0h, followed by the byte address 01h for v trip1 , 09h for v trip2 , and 0dh for v trip3 , and a 00h data byte in order to program v tripx . the stop bit following a valid write operation initiates the programming sequence. pin wp must then be brought low to complete the operation (see figure 23). the user does not have to set the wel bit in the cr register before performing this write sequence. setting a lower v tripx voltage (x = 1,2,3). in order to set v tripx to a lower voltage than the present value, then v tripx must first be ?reset? accord- ing to the procedure described below. once v tripx has been ?reset?, then v tripx can be set to the desired voltage using the procedure described in ?setting a higher v tripx voltage?. resetting the v tripx voltage (x = 1,2,3). to reset a v tripx voltage, apply the programming volt- age (vp) to the wp pin before a start condition is set up on sda. next, issue on the sda pin the slave address a0h followed by the byte address 03h for v trip1 , 0bh for v trip2 , and 0fh for v trip3 , followed by 00h for the data byte in order to reset v tripx . the stop bit following a valid wr ite operation initiates the programming sequence. pin wp must then be brought low to complete the operation (see figure 23). the user does not have to set the wel bit in the cr regis- ter before performing this write sequence. after being reset, the value of v tripx becomes a nomi- nal value of 1.7v. v tripx accuracy (x = 1,2,3). the accuracy with which the v tripx thresholds are set, can be controlled using the iterative process shown in figure 24. if the desired threshold is le ss that the present thresh- old voltage, then it must fi rst be ?reset? (see "resetting the v tripx voltage (x = 1,2,3)."). the desired threshold voltage is then applied to the appropriate input pin (v cc , v2mon or v3mon) and the procedure described in section ?setting a higher v tripx voltage? must be followed. once the desired v tripx threshold has been set, the error between the desired and (new) actual set thresh- old can be determined. this is achieved by applying v cc to the device, and then applying a test voltage higher than the desired threshold voltage, to the input pin of the voltage monitor circuit whose v tripx was programmed. for example, if v trip2 was set to a desired level of 3.0 v, then a test voltage of 3.4 v may be applied to the voltage monitor input pin v2mon. in the case of setting of v trip1 then only v cc need be applied. in all cases, ca re should be taken not to exceed the maximum input voltage limits. after applying the test volt age to the voltage monitor input pin, the test voltage can be decreased (either in discrete steps, or continuously) until the output of the voltage monitor circuit changes state. at this point, the error between the actual/measured, and desired threshold levels is calculated. sda a0h ? 01234567 scl 01234567 wp v p 01234567 figure 23. resetting the v tripx level 03h ? resets vtrip1 0bh ? resets vtrip2 0fh ? resets vtrip3 data byte 00h ? s t a r t ? all others reserved. x40231, x40233, x40235, x40237, x40239
24 fn8115.0 april 11, 2005 for example, the desired threshold for v trip2 is set to 3.0 v, and a test voltage of 3.4 v was applied to the input pin v2mon (after applying power to v cc ). the input volt- age is decreased, and found to trip the associated output level of pin v2fail from a low to a high, when v2mon reaches 3.09 v. from this, it can be calculated that the programming error is 3.09 - 3.0 = 0.09 v. if the error between the desired and measured v tripx is less than the maximum desired error, then the program- ming process may be terminated. if however, the error is greater than the maximum desired error, then another iteration of the v tripx programming sequence can be performed (using the calculated error) in order to further increase the accuracy of the threshold voltage. if the calculated error is greater than zero, then the v tripx must first be ?reset?, and then programmed to the a value equal to the previously set v tripx minus the calculated error. if it is the case that the error is less than zero, then the v tripx must be programmed to a value equal to the previously set v tripx plus the absolute value of the calculated error. continuing the previous example, we see that the cal- culated error was 0.09v. since this is greater than zero, we must fi rst ?reset? the v trip2 threshold, then apply a voltage equal to the last previously pro- grammed voltage, minus the last previously calculated error. therefore, we must apply v trip2 = 2.91 v to pin v2mon and execute the programming sequence (see "setting a higher v tripx voltage (x = 1,2,3)"). using this process, the desired accuracy for a particu- lar v tripx threshold may be attained using a succes- sive number of iterations. v tripx programming power-down ramp up vx switches? actual v tripx - desired v tripx done execute sequence v tripx reset set vx = desired v tripx execute sequence set higher v tripx new vx applied = old vx applied + | error | execute sequence reset v tripx new vx applied = old vx applied - | error | error < mde ? | error | < | mde | yes no error >mde + no yes figure 24. v tripx setting / reset sequence (x = 1,2,3) desired v tripx < present value? note: x = 1,2,3. let: mde = maximum desired error output acceptable error range mde + mde ? error = actual ? desired = error desired value x40231, x40233, x40235, x40237, x40239
25 fn8115.0 april 11, 2005 absolute maximum ratings recommended operating conditions note: stresses above those listed under ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress ra ting only and the functional operation of the device at these or any other conditions above those listed in the operational sections of t his specifica- tion is not implied. exposure to absol ute maximum rating conditions for extended periods may affect device reliability. figure 25. equivalent a.c. circuit figure 26. dcp spice macromodel parameter min. max. units temperature under bias -65 +135 c storage temperature -65 +150 c voltage on wp pin (with respect to vss) -1.0 +15 v voltage on other pins (with respect to vss) -1.0 +7 v voltage on r hx - voltage on r lx (x = 0,1,2. referenced to v ss )v cc v d.c. output current (sda,resetreset,v2fail ,v3fail )05ma lead temperature (soldering, 10 seconds) 300 c supply voltage limits (applied v cc voltage, referenced to v ss )2.77v temperature min. max. units industrial -40 +85 c v cc = 5v v2fail 100pf sda 2300 ? v3fail reset c h c l r wx 10pf 10pf r hx r lx r total c w 25pf r w (x = 0,1,2) x40231, x40233, x40235, x40237, x40239
26 fn8115.0 april 11, 2005 timing diagrams figure 27. bus timing figure 28. wp pin timing figure 29. write cycle timing t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t aa t r t hd:wp scl sda in wp t su:wp clk 1 clk 9 start scl sda t wc 8th bit of last byte ack stop condition start condition x40231, x40233, x40235, x40237, x40239
27 fn8115.0 april 11, 2005 figure 30. power-up and power-down timing figure 31. manual reset timing diagram figure 32. v2mon, v3mon timing diagram v cc t purst t r t f 0 volts v trip1 reset t rpd 0 volts t purst mr 0 volts t rpd 0 volts mr reset t purst t mrd 0 volts v cc v cc v trip1 t mrpw vx t rx t fx v tripx v rvalid vxfail t rpdx 0 volts note : x = 2,3. 0 volts 0 volts t rpdx t rpdx t rpdx v trip1 v cc x40231, x40233, x40235, x40237, x40239
28 fn8115.0 april 11, 2005 figure 33. v tripx programming timing diagram (x=1,2,3). figure 34. dcp ?wiper position? timing wp t vps v p t vpo scl sda t wc t tsu t thd v cc , v2mon, v3mon v tripx 00h t vph note : v1/v cc must be greater than v2mon, v3mon when programming. s t a r t 10101110 a c k wt 0 0 0 0 0 p1 p0 a c k s t o p a c k d7 d6 d5 d4 d3 d2 d1 d0 slave address byte instruction byte data byte scl sda time rwx (x=0,1,2) t wr r wx(n+1) r wx(n-1) r wx(n) n = tap position x40231, x40233, x40235, x40237, x40239
29 fn8115.0 april 11, 2005 d.c. operating characteristics notes: 1. the device enters the active state after any start, and remains active until: 9 clock cycles later if the device sel ect bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or t wc after a stop ending a write operation. notes: 2. the device goes into standby: 200ns after any stop, except those that initiate a high voltage write cycle; t wc after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the corr ect device select bi ts in the slave add ress byte. notes: 3. current through external pull up resistor not included. notes: 4. v in = voltage applied to input pin. notes: 5. v out = voltage applied to output pin. notes: 6. see ?ordering information? on page 36. notes: 7. v il min. and v ih max. are for reference only and are not tested notes: 8. equivalent input circuit for v xmon symbol parameter min typ max unit test conditions / notes v cc 2.7 5.5 v requires v cc > v trip1 or chip will not operate. i cc 1 (1) current into v cc pin (x4023x: active) read memory array (3) write nonvolatile memory v cc = 3.5v 0.4 1.5 ma f scl = 400khz i cc 2 (2) current into v cc pin (x4023x:standby) with 2-wire bus activity (3) no 2-wire bus activity v cc = 3.5v 50.0 50.0 a v sda = v cc mr = vss wp = vss or open/floating v scl = v cc (when no bus activity else f scl = 400khz) i li input leakage current (scl, sda, mr) 0.1 10 av in (4) = gnd to v cc . input leakage current (wp) 10 a i lo output leakage current (sda, reset, v2fail , v3fail ) 0.1 10 a v out (5) = gnd to v cc . x4023x is in standby (2) v trip1pr v trip1 programming range 2.75 4.70 v v tripx pr v tripx programming range (x = 2,3) 1.75 3.50 v v trip1 (6) pre - programmed v trip1 threshold 2.8 4.3 2.95 4.45 3.00 4.50 v factory shipped default option a factory shipped default option b v trip2 (6) pre - programmed v trip2 threshold 2.05 2.8 2.20 2.95 2.25 3.00 v factory shipped default option a factory shipped default option b v trip3 (6) pre - programmed v trip3 threshold 1.60 1.60 1.75 1.75 1.80 1.80 v factory shipped default option a factory shipped default option b t rpdx v cc , v2mon, v3mon to reset, v2fail , v3fail propagation delay (respectively) 20 s see (8) i vx v2mon input leakage current v3mon input leakage current 1 1 a v sda = v scl = v cc others = gnd or v cc v il (7) input low voltage (scl, sda, wp, mr) -0.5 0.8 v v ih (7) input high voltage (scl,sda, wp, mr) 2.0 v cc +0.5 v v olx reset, v2fail , v3fail , sda output low voltage 0.4 v i sink = 2.0ma + ? v xmon v ref x40231, x40233, x40235, x40237, x40239
30 fn8115.0 april 11, 2005 a.c. characteristics (see fi gure 27, figure 28, figure 29) a.c. test conditions nonvolatile write cycle timing capacitance (t a = 25c, f = 1.0 mhz, v cc = 5v) notes: 1. typical values are for t a = 25c and v cc = 5.0v notes: 2. cb = total capacitance of one bus line in pf. notes: 3. over recommended operating conditions, unless ot herwise specified notes: 4. t wc is the time from a valid stop condition at the end of a writ e sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless ac knowledge polling is used. notes: 5. this parameter is not 100% tested. symbol parameter 400khz min max units f scl scl clock frequency 0 400 khz t in (5) pulse width suppression time at inputs 50 ns t aa scl low to sda data out valid 0.1 0.9 s t buf time the bus free before st art of new transmission 1.3 s t low clock low time 1.3 s t high clock high time 0.6 s t su:sta start condition setup time 0.6 s t hd:sta start condition hold time 0.6 s t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 0.6 s t dh data output hold time 50 ns t r (5) sda and scl rise time 20 +.1cb (2) 300 ns t f (5) sda and scl fall time 20 +.1cb (2) 300 ns t su:wp wp setup time 0.6 s t hd:wp wp hold time 0 s cb capacitive load for each bus line 400 pf input pulse levels 0.1v cc to 0.9v cc input rise and fall times 10ns input and output timing levels 0.5v cc output load see figure 25 symbol parameter min. typ. (1) max. units t wc (4) nonvolatile write cycle time 5 10 ms symbol parameter max units test conditions c out (5) output capacita nce (sda, reset, v2fail , v3fail )8 pf v out = 0v c in (5) input capacitance (scl, wp, mr) 6 pf v in = 0v x40231, x40233, x40235, x40237, x40239
31 fn8115.0 april 11, 2005 potentiometer characteristics notes: 1. power rating between the wiper terminal r wx(n) and the end terminals r hx v ss - for any tap position n, (x = 0,1,2). notes: 2. absolute linearity is ut ilized to determine actual wiper re sistance versus, ex pected resistance = (r wx(n) (actual) - r wx(n) (expected)) = 1 ml maximum (x = 0,1,2). notes: 3. relative linearity is a measure of the error in step size between taps = r wx(n+1) - [r wx(n) + ml] = 0.2 ml (x = 0,1,2) notes: 4. 1 ml = minimum increment = r tot / (number of taps in dcp - 1). notes: 5. typical values are for t a = 25c and nominal supply voltage. notes: 6. this parameter is periodically sampled and not 100% tested. symbol parameter limits test conditions/notes min. typ. max. units r tol end to end resistance tolerance -20 +20 % in a ratiometric circuit, r total divides out of the equation and accuracy is determined by xdcp resolution. v rhx r h terminal voltage (x = 0,1,2) vss v cc v v rlx r l terminal voltage (x = 0,1,2) vss vss v r l terminal internally tied to gnd. p r power rating (1) 10 mw r total = 10k ? ( dcp0, dcp1) 5mwr total = 100k ? ( dcp2) r w dcp wiper resistance 200 400 ? v cc = 5 v, v rhx = v cc , v rlx = vss (x = 0,1,2), i w = 50 ua /500 ua (100/10k ?) . 400 1200 ? v cc = 2.7 v, v rhx = v cc , v rlx = vss (x = 0,1,2), i w = 27 ua /270 ua (100/10 k ?) . i w wiper current 4.4 ma noise mv (hz) r total = 10k ? ( dcp0, dcp1) mv (hz) r total = 100k ? ( dcp2) absolute linearity (2) -1 +1 mi (4) r w(n)(actual) - r w(n)(expected) relative linearity (3) -1 +1 mi (4) r w(n+1) - [r w(n) + mi ] r total temperature coefficient 300 ppm/c r total = 10k ? ( dcp0, dcp1) 300 ppm/c r total = 100k ? ( dcp2) ratiometric temperature coefficient 30 ppm/c (voltage divider configuration) c h /c l / c w potentiometer capacitances 10/10/25 pf see figure 26. t wr wiper response time 200 s see figure 34. x40231, x40233, x40235, x40237, x40239
32 fn8115.0 april 11, 2005 v tripx (x = 1,2,3) programming parameters (see figure 33) notes: 100% tested. reset, v2fail , v3fail output timing. (see figure 30, figure 31, figure 32) notes: 1. see figure 31 for timing diagram. notes: 2. see figure 25 for equivalent load. notes: 3. this parameter describes the lowest possible v cc level for which the outputs reset, v2fail , and v3fail will be correct with respect to their inputs (v cc , v2mon, v3mon). notes: 4. from mr rising edge crossing v ih , to reset rising edge crossing v oh . notes: 5. equivalent input circuit for v xmon parameter description min typ max units t vps v tripx program enable voltage setup time 10 s t vph v tripx program enable voltage hold time 10 s t tsu v tripx setup time 10 s t thd v tripx hold (stable) time 10 s t vpo v tripx program enable voltage off time (between successive adjustments) 1ms t wc v tripx write cycle time 5 10 ms v p programming voltage 10 15 v v ta v tripx program voltage accuracy programmed at 25c.) -100 +100 mv v tv v trip program variation after programming (-40 - 85c). (programmed at 25c.) -25 +10 +25 mv symbol description condition min. typ. max. units t purst power-on reset delay time pup1 = 0, pup0 = 0 25 50 75 ms pup1 = 0, pup0 = 1 50 100 150 ms pup1 = 1, pup0 = 0 100 200 300 ms pup1 = 1, pup0 = 1 150 300 450 ms t mrd (31)(2) mr to reset propagation delay see (1)(2)(4) 5 s t mrdpw mr pulse width 500 ns t rpdx v cc , v2mon, v3mon to reset, v2fail , v3fail propagation delay (respectively) see (5) 20 s t fx v cc , v2mon, v3mon fall time 20 mv/ s t rx v cc , v2mon, v3mon rise time 20 mv/ s v rvalid v cc for reset, v2fail , v3fail valid (3) . 1v + ? t rpdx = 20s worst case v xmon v ref output x40231, x40233, x40235, x40237, x40239
33 fn8115.0 april 11, 2005 appendix 1 dcp1 (100 tap) tap position to data byte translation table tap position data byte decimal binary 0 0 0000 0000 1 1 0000 0001 . . . . . . 23 23 0001 0111 24 24 0001 1000 25 56 0011 1000 26 55 0011 0111 . . . . . . 48 33 0010 0001 49 32 0010 0000 50 64 0100 0000 51 65 0100 0001 . . . . . . 73 87 0101 0111 74 88 0101 1000 75 120 0111 1000 76 119 0111 0111 . . . . . . 98 97 0110 0001 99 96 0110 0000 x40231, x40233, x40235, x40237, x40239
34 fn8115.0 april 11, 2005 appendix 2 dcp1 (100 tap) tap position to data byte translation algorithm example. unsigned dcp1_tap_position(int tap_pos) { int block; int i; int offset; int wcr_val; offset = 0; block = tap_pos / 25; if (block < 0) return ((unsigned)0); else if (block <= 3) { switch(block) { case (0): return ((unsigned)tap_pos) ; case (1): { wcr_val = 56; offset = tap_pos - 25; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned) wcr_val); } case (2): { wcr_val = 64; offset = tap_pos - 50; for (i=0; i<= offset; i++) wcr_val++ ; return ((unsigned) wcr_val); } case (3): { wcr_val = 120; offset = tap_pos - 75; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned) wcr_val); } } } return((unsigned)01100000); } x40231, x40233, x40235, x40237, x40239
35 fn8115.0 april 11, 2005 16-lead plastic, soic (300-mil body), package code s16 note: all dimensions in inches (in parentheses in millimeters) 0.014 (0.35) 0.020 (0.51) pin 1 pin 1 index 0.050 (1.27) 0.403 (10.2 ) 0.413 ( 10.5) (4x) 7 0.420" 0.050" typical 0.030" typical 16 places footprint 0.010 (0.25) 0.020 (0.50) 0.0075 (0.19) 0.010 (0.25) 0 - 8 x 45 0.050" typical 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) 0.015 (0.40) 0.050 (1.27) x40231, x40233, x40235, x40237, x40239
36 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8115.0 april 11, 2005 device preset (factory shipped) v tripx threshold levels (x = 1,2,3) a = optimized for 3.3 v system monitoring ? 3.3 10%, 2.5 10%, 1.8 v +10%/-0% b = optimized for 5 v system monitoring ? 5.0 10%, 3.3 10%, 1.8 v +10%/-0% temperature range i = industrial -40 c to +85 c package s16 = 16-lead widebody soic (300 mil) x4023x pt - y ? for details of preset threshold values , see "d.c. operating characteristics" ordering information x device 1 x40231 3 x40233 5 x40235 7 x40237 9 x40239 x40231, x40233, x40235, x40237, x40239

▲Up To Search▲

Price & Availability of X40231S16I-BT1

	To Download X40231S16I-BT1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .